Wafer develop 까지 완료된 패턴 날리는 방법

Semiconductor manufacturers are increasingly adopting negative tone patterning for their leading-edge lithography applications due to the inherently superior contrast and imaging quality. However, negative tone patterning presents new challenges related to photoresist (resist) shrinkage that can impact wafer patterning performance if not appropriately compensated with reticle feature adjustments. Building on our computational lithography expertise, we developed a new physical resist shrinkage model to improve the accuracy of patterning predictions.

The case for negative tone patterning and emerging challenges
Since the 1980s, positive tone patterning has been the semiconductor industry workhorse due to its well established capabilities and extensive investment in positive photoresist chemistry and processing. However, since the early 2000s, scientists have known that negative tone patterning can be fundamentally superior to positive tone patterning for low k1 imaging. But, it wasn’t until the last few years with the advent of high-resolution negative tone photoresists that the industry was able to realize this inherent advantage. Consequently, semiconductor manufacturers are increasingly adopting negative tone patterning for their leading-edge lithography applications.

Due to electromagnetic effects in the mask, it is easier to print very small features — e.g. small contact holes and trenches — by making them dark rather than bright. This is enabled by the use of negative-tone development (NTD) where resist areas exposed by light remain on the wafer (see illustration). Another way of saying this, the use of NTD results in higher image contrast and in a larger process window.

Yet what we gain in resolution, we may lose in pattern accuracy. Depending on the pattern shape and surrounding features, shrinkage during the post-exposure bake can significantly affect the final patterns printed on the wafer.

ASML’s engineers studied these NTD process shrinkage effects and developed a new model that enables our customers to more accurately predict what will happen on the wafer.

“If we can accurately predict these effects, we can correct for them. If we can correct for them, then we can enable improved patterning at the wafer level,” explains Keith Gronlund, director of product marketing, Process Window Enhancement solutions.

A new model is born
In a perfect world, we would pattern flawless squares and rectangles because that’s how chip design elements are drawn on a mask. However, after light passes through the optical elements in a scanner and the photoresist is processed, the result is quite different due to the optical effect of diffraction as well as various resist effects including resist shrinkage.

How can we compensate for all these changes? Return to the mask design. Optical proximity corrections (OPC) — also known as “decorations” and “sub-resolution assist” features — are used to pre-distort mask features in order to yield printed wafer images that more accurately match the original design intent. What’s the catch? You need accurate models to know what the wafer pattern is resulting from a given mask pattern, and to know exactly how to make changes to the reticle design.

There have always been two types of models — empirical and physical — used in software to simulate and make changes to the reticle design, so that the printed patterns match the intent. Generally, an empirical model has a simpler mathematical form and is easier to implement in computer software, but it is based on observations and only applies to a limited range of situations. On the other hand, a physical model is much more complex.

“After extensively studying the resist shrinkage effects and seeing the failure of empirical models, we decided to take on the challenge of developing a complex physical model,” said Peng Liu, model expert at ASML. “Tapping into our computational lithography expertise, we built a solution based on complicated mathematical equations rooted in physics, resulting in a more accurate physical model that we could apply to a wide range of situations.”

ASML’s new physical resist shrinkage (PRS) model delivers modified OPC recommendations for the NTD process. Already in evaluation by multiple semiconductor manufacturers, the PRS model has led to a 35% improvement in the difference between modeled critical dimensions (CD) and measured wafer CDs, as well as a 59% improvement in the overall model accuracy compared to existing methods.

Why does this matter?
As technology nodes continue to shrink, so does the process window. Without the use of models to accurately capture critical process effects, engineers can’t ensure accurate wafer patterning performance, and chipmakers will experience pattern defects and yield loss. ASML’s OPC solutions that incorporate the NTD PRS model enable the next-generation nodes by improving CD control and enlarging the process window. Using these tools, chipmakers can transition more quickly to future nodes, while enabling optimal yield levels.

“There will always be variation in manufacturing, but the more robust the process, the larger the margin of error. And, that is exactly what our NTD PRS model enables,” concludes Keith.